Loop Filter

1. The ADPLL filter is needed to remove any unwanted high frequency components which might pass out of the phase detector and appear in the DCO tune line.

2. If the filter is not designed correctly then oscillations can build up around the loop, and large signals will appear on the tune line.

3. Without a loop filter you would almost certainly be feeding a waveform rather than a steady voltage back to the DCO and the result would be unpredictable and unstable at the very least. If the loop time constant is too short you will get residual signal on the control voltage causing FM on the DCO but the reaction (lock) time would fast.

Frequency Divider

1. A frequency divider, also called a clock divider or scaler or prescaler, is a circuit that takes an input signal of a frequency, fin, and generates an output signal of a frequency
                      fout=fin/n
                      where n is an integer.

2. Frequency divider is an important building block in today’s RFIC and microwave circuits because it is an integral part of the phase-locked loop (PLL) circuit.

Phase Detector

A  phase  detector  or phase comparator  is a frequency mixer, analog multiplier  circuit that generates a voltage signal which represents the difference in phase between two signal inputs. It is an essential element of the Phase locked loop (PLL). Detecting phase differences is very important in many applications, such as motor  control, radar  and telecommunication system.

Digital Controll Oscillator (DCO)

The Time to digital converter (TDC) used in this project is composed of two parts for count the reference clock and DCO clock period.The proposed DCO employs a new approach to increase the delay tuning range using digitally controlled pass transistor arrays and Schmitt trigger-based inverters.Compared to the conventional DCO, the proposed DCO saves approximately 15% power consumption.However, this DCO design has a limited operating frequency range, which is improved in this project by employing the fixed delay blocks and 4:1 Mux which can give 4 times larger operating range. It work for multimode frequency. It capture different frequencies between 590 MHz to 840 MHz.

Introduction

This brief presents a frequency estimation algorithm (FEA) for an All-Digital Phase-Locked Loop (ADPLL) instead of the traditional binary frequency-searching algorithm. Based on the proposed FEA and a new fast-lock scheme, a fast-lock engine is designed to improve the lock-in time of an ADPLL design with two referenced clock cycles. An implementation of the proposed ADPLL design is realized by utilizing United Microelectronics Corporation (UMC) 0.18-μm1P6M CMOS technology.